1. Field of the Invention
The present invention relates to a metallization process for fabrication of interconnect, and especially to a damascene process using anti-reflective coating to improve its process window.
2. Description of the Prior Art
For building an integrated circuit operating with desired action, it is necessary to fabricate many active devices on a single semiconductor substrate. Various kinds of devices with different functions, such as transistors, resistors and capacitors, are formed together. Today, we usually build hundreds of thousands of semiconductor devices on a single chip. Each of the devices on the substrate must be electrically isolated from the others to ensure their individual function, and, specific devices must be electrically interconnected so as to implement the whole desired circuit function.
In order to construct the interconnection and contact among all the active devices, a metallization process is employed. At an early stage, single layer metallization process provides all the designed connection. But, as the integrated circuit technology trend toward increase of the integration and decrease of the size, the surface of the chip cannot provide enough area to build all the interconnects needed. It must be designed more than one level of interconnects. The multilevel-interconnect technology is thus developed to meet this demand.
A conventional multilevel-interconnect technology is performed by utilizing a metal patterning to form the interconnecting lines. On the semiconductor substrate with active devices and underlying interconnect layer built in, the metal plug pattern is formed by dielectric layer deposition, photolithography and etching for patterning. After stripping the photoresist for plug pattern, a metal layer with metal plug is deposited on the semiconductor substrate. A metal line photolithography followed by an anisotropic etching is then performed to etch the metal layer to formed the interconnect layer.
Due to the difficulty of metal patterning, a new technique named damascene process is developed to be the tendency of the multilevel-interconnect technology. The damascene process employs the inter-layer dielectric patterning instead of the metal patterning. That is, after the plug process is done, another inter-layer dielectric is deposited, and the metal line pattern is opened in the inter-layer dielectric. The interconnection metal deposition with etching back then follows to refilled the metal line trenches. One level of interconnects is thus formed and the difficulty of metal patterning can be avoided.
Another improved method called dual damascene process is applied for simplify the manufacture processes. For the dual damascene process, the plug material is deposited at the same step of the interconnection metal line deposition. It means that the plug and interconnection line pattern are formed together after one single inter-layer dielectric deposition. And, of course, it reduces one times of inter-layer dielectric deposition, metal deposition and planarization respectively in comparison with single damascene process where the plug is formed individually.
The damascene and dual damascene processes fabricate the interconnect pattern using the dielectrics etching instead of the metal etching so as to avoid the difficulty of the latter one. But the damascene and dual damascene processes have their own problems. The interconnecting line width varies at the places where the upper lines cross over the underlying conductive lines. It's because the photoresist line pattern on transparent dielectric layer is easily influenced by standing wave effects and the under layer scattering due to diffraction and reflection. As referring to a cross-sectional view of a semiconductor wafer shown in FIG. 1, wherein a underlying conductive line 2 and a inter-layer dielectric 4 are built, a photoresist 6 is coated on the inter-layer dielectric 4 and exposed for a interconnect line pattern with a photo mask 8. The photo mask 8 has a width w the same as the desired photoresist line width, and therefore as the designed dielectric one between two adjacent interconnecting lines in the same level. In the exposure process, the exposure light 10 scattered from the underlying conductive line 2 to the photoresist 6 will increase the exposed photoresist region and cause the photoresist line width decreasing from value w to value x after development. This phenomena causes notches of photoresist lines over topography and an interconnecting line width variation from value y to value z, which will result in a metal bridge problem.
The metal bridge problem is severe when the dielectric line width is narrow in design rule, especially when below deep submicron range. FIG. 2 shows a top view of a semiconductor wafer, wherein the AA' cross section is illustrated in FIG. 1. The regions 20 represent the underlying conductive lines marked 6 previously in FIG. 1. The patterned photoresist lines 2, which are marked 6 in FIG. 2 and in FIG. 1, become narrow right over the underlying conductive lines 2 from a designed line width of value w to the final value x. Then the line width of the interconnecting lines represented by regions 24 varies from a desired value y to a larger value z. The notches 26 of photoresist lines, which will result in dielectric notches finally, may be so narrow that the dielectric lines break and the insulated metal lines come into contact with each other. Even if the dielectric lines do not break, it may be still too narrow that the tunneling effect will arise, and thus the metal bridges could be generated here whenever the dielectric lines break or not.